1. Field of the Invention
The present invention relates generally to dielectric layers within microelectronics fabrications. More particularly, the present invention relates to doped silicate glass dielectric layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed employing microelectronics substrates upon which are formed patterned conductor layers which are separated by dielectric layers. Within microelectronics fabrications in general, a particularly common dielectric material which is employed in forming dielectric layers within microelectronics fabrications is a boron and/or phosphorus doped silicate glass dielectric material, such as a boro silicate glass (BSG) dielectric material, a phospho silicate glass (PSG) dielectric material or a boro phospho silicate glass (BPSG) dielectric material.
Boron and/or phosphorus doped silicate glass dielectric materials are desirable when employed in forming dielectric layers within microelectronics fabrications since such boron and/or phosphorus doped silicate glass dielectric materials are readily reflowed at comparatively low temperatures to form reflowed boron and/or phosphorus doped silicate glass dielectric layers which can typically substantially planarize irregular substrate surfaces within microelectronics fabrications within which they are formed. Typically, although not exclusively, boron and/or phosphorus doped silicate glass dielectric layers are formed within microelectronics fabrications through a chemical vapor deposition (CVD) method, either thermally activated or plasma activated, employing a silicon source material such as but not limited to tetra ethyl ortho silicate (TEOS) or silane, along with a suitable boron and/or phosphorus dopant source material.
While boron and/or phosphorus doped silicate glass dielectric layers formed through chemical vapor deposition (CVD) methods employing suitable silicon source materials in conjunction with suitable boron and/or phosphorus source materials are thus desirable in the art of microelectronics fabrication, boron and/or phosphorus doped silicate glass dielectric layers formed through chemical vapor deposition (CVD) methods employing suitable silicon source materials in conjunction with suitable boron and/or phosphorus source materials are not entirely without problems within microelectronics fabrication. In particular, it is known in the art of microelectronics fabrication that doped silicate glass layers when formed through chemical vapor deposition (CVD) methods, patterned through conventional anisotropic patterning methods and subsequently isotropically etched with isotropic etchants containing hydrofluoric acid, such as but not limited to dilute hydrofluoric acid etchants and buffered oxide etchants (ie: aqueous hydrofluoric acid and ammonium fluoride mixtures), often exhibit irregular via sidewall profiles characterized by increased isotropic etching and void formation at the base of those irregular via sidewall profiles. A pair of schematic cross-sectional diagrams illustrating the results of forming a pair of such irregular sidewall profile vias defined by a series of such isotropically etched anisotropically patterned doped silicate glass dielectric layers is shown in FIG. 1 and FIG. 2.
Shown in FIG. 1 is a substrate 10 having formed therein a pair of contact regions 12a and 12b. Access to the pair of contact regions 12a and 12b is through a pair of anisotropically patterned contact vias 15a and 15b defined by a series of anisotropically patterned doped silicate glass dielectric layers 14a, 14b and 14c. The anisotropically patterned doped silicate glass dielectric layers 14a, 14b and 14c are in turn formed through etching a corresponding blanket doped silicate glass dielectric layer within an anisotropic etching plasma 18, while employing a series of patterned photoresist layers 16a, 16b and 16c as a series of photoresist etch mask layers.
Referring now to FIG. 2, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is a schematic cross-sectional diagram of a microelectronics fabrication otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein: (1) the patterned photoresist layers 16a, 16b and 16c have been stripped from the microelectronics fabrication; and (2) the microelectronics fabrication has subsequently been isotropically etched within an isotropic etchant, typically although not exclusively a hydrofluoric acid containing isotropic etchant. Isotropic etching of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 to provide the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 is commonly employed within microelectronics fabrications prior to forming a pair of contact layers within the pair of anisotropically patterned contact vias 15a and 15b.
As is illustrated within the schematic cross-sectional diagram of FIG. 2, the resulting isotropically etched anisotropically patterned contact vias 15a' and 15b' defined by the series of isotropically etched anisotropically patterned doped silicate glass dielectric layers 14a', 14b' and 14c' have irregularly formed via sidewalls characterized by a series of voids 20 formed at the junctures of the series of isotropically etched anisotropically patterned doped silicate glass dielectric layers 14a', 14b' and 14c' with the contact regions 12a and 12b within the substrate 10.
Voids which are formed when isotropically etching anisotropically patterned vias which in turn are formed through doped silicate glass dielectric layers within microelectronics fabrications (such as the voids 20 within the isotropically etched anisotropically patterned vias 15a' and 15b' defined by the isotropically etched anisotropically patterned doped silicate glass dielectric layers 14a', 14b' and 14c' within the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2) are undesirable within microelectronics fabrication. In particular, when such vias are separated by particularly narrow widths of isotropically etched anisotropically patterned doped silicate glass dielectric material the voids formed therein may cause contact layer bridging between contact layers subsequently formed within adjacent vias. It is thus towards the goal of forming within microelectronics fabrications void free vias incident to isotropically etching anisotropically patterned vias which are formed through doped silicate glass dielectric layers within microelectronic fabrications that the present invention is generally directed.
Various methods have been disclosed in the art of microelectronics fabrication for forming dielectric layers with novel and desirable properties within microelectronics fabrications.
For example, Wang et al., in U.S. Pat. No. 4,892,753, discloses a plasma enhanced chemical vapor deposition (PECVD) method for forming a silicon oxide dielectric layer within an integrated circuit microelectronics fabrication while employing tetra ethyl ortho silicate (TEOS) as a silicon source material. The method employs a comparatively high deposition pressure of from about 1 to about 50 torr to form the plasma enhanced chemical vapor deposited (PECVD) silicon oxide layer with improved step coverage upon a topographic substrate layer, and with lower stress.
In addition, Monkowski et al., in U.S. Pat. No. 5,104,482, discloses a method for forming a boro phospho silicate glass (BPSG) dielectric layer upon a topographic substrate layer within an integrated circuit microelectronics fabrication. The method employs a sufficiently high reactant velocity and a sufficiently high reactant deposition temperature to provide simultaneous deposition and viscoelastic flow properties of the boro phospho silicate glass (BPSG) dielectric layer, thus providing substantially void free topographic planarization of the topographic substrate layer with the boro phospho silicate glass (BPSG) dielectric layer.
Finally, Dean et al., in U.S. Pat. No. 5,643,838, also discloses a plasma enhanced chemical vapor deposition (PECVD) method for forming a silicon oxide dielectric layer upon a topographic substrate layer within a microelectronics fabrication while employing tetra ethyl ortho silicate (TEOS) as a silicon source material. Through the method the silicon oxide dielectric layer is formed void free upon the topographic substrate layer with sufficiently attenuated moisture and silanol presence within the silicon oxide dielectric layer such that there is avoided integrated circuit device degradation within an integrated circuit within which is formed the silicon oxide dielectric layer.
Desirable within the art of microelectronics fabrication are methods and materials through which isotropically etched anisotropically patterned vias defined by isotropically etched anisotropically patterned doped silicate glass dielectric layers within microelectronics fabrications may be formed without voids within the sidewalls of those isotropically etched anisotropically patterned vias. More particularly desirable within the art of integrated circuit microelectronics fabrication are methods and materials through which isotropically etched anisotropically patterned vias defined by isotropically etched anisotropically patterned doped silicate glass dielectric layers within integrated circuit microelectronics fabrications may be formed without voids within the sidewalls of those isotropically etched anisotropically patterned vias. It is towards the foregoing goals that the present invention is both generally and more specifically directed.